International Journal of Scientific Research and Engineering Development

International Journal of Scientific Research and Engineering Development


( International Peer Reviewed Open Access Journal ) ISSN [ Online ] : 2581 - 7175

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๐Ÿ“‘ Paper Information
๐Ÿ“‘ Paper Title Design and Analysis of an 8-Bit Parallel-In Parallel-Out Register Using an 18-Transistor Hybrid Flip-Flop for Low-Power Applications
๐Ÿ‘ค Authors Ragala Harish, Jammanamadaka Vasanth, Buddala Nagendra Babu, Ravada Charanya Priya, Kanugula Dhana Lakshmi, Dr.Ch. Venkata Rao
๐Ÿ“˜ Published Issue Volume 9 Issue 2
๐Ÿ“… Year of Publication 2026
๐Ÿ†” Unique Identification Number IJSRED-V9I2P314
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๐Ÿ“ Abstract
In contemporary VLSI systems, efficient storage elements remain central to achieving both high operating speed and minimal energy dissipation. This paper presents the complete design and performance evaluation of an 8-bit parallelin parallel-out (PIPO) register constructed from a partially static 18-transistor (18T) hybrid flip-flop. The chosen flipflop merges the speed advantage of pass-transistor logic in the input stage with the robustness of static CMOS inverters in the storage stage, thereby eliminating many of the contention and leakage problems typical of purely dynamic or conventional master-slave topologies. Eight identical 18T hybrid flip-flops are connected in parallel under a single global clock, enabling simultaneous capture and transfer of 8-bit data without additional clock-gating circuitry. The entire architecture has been realized at the transistor level in 65 nm CMOS technology using Tanner EDA tools. Extensive transient simulations confirm correct edge-triggered operation, stable data retention across multiple clock cycles, and clean output waveforms devoid of glitches. Measured results show an average power consumption of 8.8179 ยตW for the complete 8-bit register, a clock-to-Q propagation delay of 37.6967 ps, and a power-delay product of 331.87 fJ. These figures represent a clear improvement over several reported static, TSPC, and contention-free flip-flop-based registers simulated under comparable conditions. The design therefore offers a practical, compact, and energy-efficient solution suitable for high-speed data-path blocks, register files, and lowpower embedded processors.
๐Ÿ“ How to Cite
Ragala Harish, Jammanamadaka Vasanth, Buddala Nagendra Babu, Ravada Charanya Priya, Kanugula Dhana Lakshmi, Dr.Ch. Venkata Rao,"Design and Analysis of an 8-Bit Parallel-In Parallel-Out Register Using an 18-Transistor Hybrid Flip-Flop for Low-Power Applications" International Journal of Scientific Research and Engineering Development, V9(2): Page(2139-2145) Mar-Apr 2026. ISSN: 2581-7175. www.ijsred.com. Published by Scientific and Academic Research Publishing.