International Journal of Scientific Research and Engineering Development

This paper presents a detailed study on the design and implementation of a parallel proportional–integral repetitive (PIR) controller for harmonic mitigation in three‑phase boost power factor correction (PFC) rectifiers. A dual‑loop control architecture is adopted, consisting of an inner current loop and an outer voltage loop. The inner loop employs a conventional PI regulator operating in parallel with a repetitive controller to ensure rapid current tracking and rejection of periodic disturbances, while the outer loop maintains the dc‑link voltage at the desired value. The mathematical models of the rectifier and control loops are derived, and controller parameters are selected to achieve stability and high power quality. Simulation experiments conducted in MATLAB/Simulink demonstrate that the proposed PIR scheme dramatically reduces total harmonic distortion (THD), improves the input power factor, and enhances dynamic performance compared to a standard PI controller. Representative results illustrate that the input current waveform becomes nearly sinusoidal, THD is reduced from over 26 % to under 3 %, and the power factor approaches unity under varying load and grid conditions.