International Journal of Scientific Research and Engineering Development

The growing deployment of cryptography in cloud services, embedded devices and the Internet of Things has triggered renewed interest in hardware acceleration. Traditional complementary metal–oxide–semiconductor (CMOS) cryptographic engines provide high throughput but dissipate significant power because their Boolean gates irreversibly destroy information. Landauer’s principle asserts that erasing one bit of information dissipates at least (kT) joules of heat, where (k) is Boltzmann’s constant and (T) the absolute temperature. Reversible logic gates preserve information and in principle can operate with asymptotically zero energy dissipation [1],[2]. Recent work has shown that reversible implementations of classical ciphers can be realised on field‑programmable gate arrays (FPGAs) using Toffoli and Fredkin gates [8]. This paper proposes a novel reconfigurable reversible gate (RRG) encryption architecture that supports symmetric cryptography with low power and resource overhead. The design cascades thirteen reversible gates to implement key scheduling, encryption and decryption, and it can be reconfigured dynamically for different cipher parameters. We implement the architecture on an FPGA, evaluate power, delay and resource utilisation for various operand widths, and compare the results with conventional CMOS designs. The RRG demonstrates lower dynamic power consumption and shorter critical paths than traditional implementations while maintaining correct cryptographic functionality.